Date 22,23,29,30.12.2019
Price 6125 + VAT /20 Tcs
DURATION 4 Days

Course Overview

PCI Express is the open standards- based successor to PCI and its variants for server- and client-system I/O interconnects. Unlike PCI and PCI-X, which are based on 32- and 64-bit parallel buses, PCI Express uses high-speed serial link technology similar to that found in Gigabit Ethernet, Serial ATA (SATA), and Serial-Attached SCSI (SAS). PCI Express reflects an industry trend to replace legacy shared parallel buses with high-speed point-to-point serial buses.

Prerequisite:

Experience of a high speed digital bus like PCI / PCI-X is strongly recommended.

In this training we will discuss and cover the following

Packet switching benefits compared to shared busses are highlighted

  • The course explains the various traffic types that PCI Express supports
  • The use of virtual channels to match Quality of Service requirements is explained
  • The course describes the discovery sequence required to initialize the switches
  • The course details the various stages of the physical layer : 8b10b and 128/130b coding, scrambling, elastic buffer, clock recovery and link training sequence
  • The course highlight the differences between the 4 generations of PCI Express 

 

Course Outline:

1. Introduction to PCI Express
• PCI express as PCI/PCI-X evolution
• PCIe System overview (topology, links , type of devices)
• Transactions types (Mem,IO,CFG ,Msg)
• PCI Express layers’ architecture

– TLP, DLLP and Ordered Set Packet Format Overview

• PCIe link performance – MPS effect and protocol overheads
• DMA operation example

2. Debugging a PCI Express System
• Compliance lists
• PCie protocol debug tools from Lecroy

– Trace analyzes will be done during different part of training

• Physical layer debug

3. Configuration Space Overview
• Type 0 and Type 1 Headers, Capability and Extended Capability
• Bus Enumeration
• CFG Access Mechanism (Legacy and ECAM)

4. Address Space and Transaction Routing
• Memory space concept
• BARs mechanism
• Resizable BARs (new in 2.1)
• PCI-to-PCI bridges routing support
• Routing in PCIe switches
• Access Control Services (ACS) (new in 2.1)

5. Transaction layer functionality
• Format of TLPs
• Multicasting (new in 2.1)
• Atomic Operations (new in 2.1)
• TLP Processing Hints (TPH) and Steering Tags(new in 2.1)
• Lightweight Notification (new in 3.1)
• Precision Time Measurement (PTM) (new in 3.1)
• Protocol Multiplexing (PMUX) (new in 2.1)

6. Quality of Service
• TC/VC Mapping
• VC Arbitration
• Port Arbitration
• VC capability

7. Transaction Ordering
• PCI Producer / Consumer model
• Relaxed ordering
• PCI Express transaction ordering rules

8. Format of DLLPs

9. Flow Control
• Overview, transmit credit principle
• Related counters
• Credit update frequency

10. ACK / NAK Protocol
• Acknowledgement objectives
• Counters / timers present in the transmitter and the receiver
• Sequences
• Cut-through operation

11. Physical Layer (Gen1 and Gen2)
• 8-bit / 10-bit coding
• Ordered sets
• Byte stripping
• Scrambling
• Elastic buffer operation

12. Physical Layer (Gen3 and Gen4)
• 128b/130b coding
• Ordered Set Blocks and Data Blocks
• Data Streams and Packet Framing

13. Physical Layer Electrical (Gen1-4)
• PCie channel
• Clock schemes and jitter budgets for SSC and SRIS
• Gen2  De-emphasis
• Gen3/4 Equalization
• Gen4 RX Margining
• Support for Retimers14. Link Initialization and Training (LTSSM)
• Link Up flow and Recovery
• Speed Change
• Equalization Training
• Power states overview
• Hot Reset, Disable and Loopback states15. Power Management
• Device Power States and DPA
• Link Power States and ASPM
• Power Management messaging (PME, Beacon and #WAKE)
• Optimized Buffer Flush Fill (OBFF), Latency Tolerance Reporting (LTR) (new in Gen2.1)
• L1 Sub-States (L1.1 and L1.2) (new in Gen3.1)
• Emergency Power Reduction with PWRBRK Signal(new in Gen4)16. Error Management
• General principles
• PCI-like error management
• PCI Express basic error management
• PCI Express advanced error capability
• Internal error reporting
• Downstream Port Containment (DPC) and Enhanced DPC (new in Gen3.1)17. Configuration space and resources allocation
• PCI-compatible registers and PCIe capabilities
• Enhanced Configuration Access Mechanism
• RC structure and RCRB
• PCI Express enumeration
• Device Readiness Status (DRS) and Function Readiness Status (FRS) (new in Gen3.1)
• Flattening Portal Bridge (FPB) (new in Gen4)
• Hierarchy ID Reporting (new in Gen4)
• Designated Vendor-Specific Extended Capability (DVSEC) (new in Gen4)18. System Resets
• Conventional Reset Mechanisms: Cold, Warm and Hot Reset

19. Hot plug/unplug
• Managed plug/unplug flows
• Surprise removal

20. Introduction to PCIe virtualization 
• Alternative Routing-ID Interpretation (ARI)
• VT-d overview
• Address translation tables and flows
• ATS and ATC
• SR-IOV device overview
• PF and VF discovery and configuration
• PF/VF configuration space
• FLR
• SR-IOV power management
• Process Address Space ID (PASID)

21. Summary

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