Price 5090 + VAT
DURATION 3 Days

Course Overview

Learn when and how to apply power & signal integrity techniques to high-speed interfaces between components. This comprehensive course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics HyperLynx. Other topics include managing PCB effects and on-chip termination. This course balances lecture modules with instructor demonstrations and practical hands-on labs.

Level:

Connectivity 3

Who should attend?

Digital designers, board layout designers, or scientists, engineers, and technologists seeking to implement Xilinx solutions. Also end users who want to understand how to implement high-speed interfaces without incurring the signal integrity problems related to timing, crosstalk, and overshoot or undershoot infractions.

Prerequisite:

Familiarity with high-speed PCB concepts

  • Basic knowledge of digital and analog circuit design
  • ISE® tool knowledge is helpful

 

Software Tools:

Mentor Graphics HyperLynx 8.0 or later

Skills Gained: After completing this training, you will be able to:

  • Describe signal integrity effects
  • Describe power integrity effects
  • Predict and overcome signal integrity challenges
  • Simulate signal integrity effects
  • Verify and derive design rules for the board design
  • Apply signal integrity techniques to high-speed
  • Supply the FPGAs with power
  • Handle thermal aspects 

 

Lab Description:

Lab 1: Invoking HyperLynx – Become familiar with signal integrity tools. Use HyperLynx for schematic entry, modeling, and simulation. Modify a standard IBIS model to define a driver and then use its stackup editor to define a PCB.

Lab 2: Reflection Analysis – Define a circuit and run various simulations for effects of reflection.

Lab 3: Crosstalk Analysis – Using simulation, analyze circuit topology and PCB data for strategies to minimize crosstalk.

Lab 4: Power Prediction – Estimate initial power requirements using an Excel spreadsheet, then use XPower Analyzer to accurately predict board power needs.

Lab 5: I/O Pin Planning – Use the PlanAhead software to identify pin placement and implement pin assignments.

Lab 6: Thermal Design – Determine maximum junction temperature and calculate acceptable thermal resistance

Course Outline:

Part 1 – Signal Integrity

1. Signal Integrity Introduction

2. Transmission Lines

3. IBIS Models and SI Tools
Lab 1:Invoking HyperLynx

4. Reflections
Lab 2:Reflection Analysis

5. Crosstalk
Lab 3:Crosstalk Analysis

6. Signal Integrity Analysis

7. Signal Integrity Summary

Part 2– Power Integrity

8. Introduction to PDN Design

9. Power Distribution Vias, Planes, Bypass Capacitors

10. Capacitors and mounting inductance

11. Spreading inductance in planes

12. Capacitor value selection is important

13.Designing for Acceptable Ground Bounce/SSO/SSN

14. DC/DC Power Supply: Switching vs. non-Switching

15. Power Supply Issues in the real world
Lab 4:Power Prediction

16. Power Summary

Part 3 – Board Design

17. Board Design Introduction

18. Signal Interfacing: Interfacing in General

19. Signal Interfacing: FPGA-Specific Interfacing
Lab 5: I/O Pin Planning

20. Die Architecture and Packaging

21. PCB Details

22. Thermal Aspects
Lab 6: Thermal Design

23. Tools for PCB Planning and Design

24. Board Design Summary

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