Start Date: 15/02/2023

Price 8,232 ILS
/ 28 Tcs


Course Overview

This comprehensive course is a thorough introduction to SystemVerilog constructs for verification. This class addresses writing testbenches to verify your design under test (DUT) utilizing the new constructs available in SystemVerilog. Object-oriented modeling, new data types, re-usable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI) are all covered. The information gained can be applied to any digital design verification approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts.
In this four-day course, you will gain valuable hands-on experience. Incoming students with a Verilog background will finish this course empowered with the ability to more efficiently verify designs.



Who should attend?

Hardware and verification engineers and FPGA designers and logic designers.


Experienced Verilog user or completion of the Designing with Verilog course.
Verilog design experience or completion of Designing with Verilog.

Skills Gained: After completing this training, you will be able to:

▪ Describe the features and benefits of using SystemVerilog for RTL design
▪ Identify the new data types supported in SystemVerilog
▪ Use an enumerated data type for coding a finite state machine (FSM)
▪ Explain how to use structures, unions, and arrays
▪ Describe the new procedural blocks and analyze the affected synthesis results
▪ Define the enhancements and ability to reuse tasks, functions, and packages
▪ Identify how to simplify module definitions and instantiations using interfaces
▪ Examine how to efficiently code in SystemVerilog for FPGA design simulation and synthesis
▪ Describe the advantages and enhancements to SystemVerilog to support verification
▪ Define the new data types available in SystemVerilog
▪ Analyze and use the improvements to tasks and functions
▪ Discuss and use the various new verification building blocks available in SystemVerilog
▪ Describe object-oriented programming and create a class-based verification environment
▪ Explain the various methods for creating random data
▪ Create and utilize random data for generating stimulus to a DUT
▪ Identify how SystemVerilog enhances functional coverage for simulation verification
▪ Utilize assertions to quickly identify correct behavior in simulation
▪ Identify how the direct programming interface can be used with C/C++ in a verification environment.

Course Outline:

Day 1
▪ Introduction to SystemVerilog {Lecture}
▪ Data Types {Lecture, Lab, Demo}
▪ User-Defined and Enumerated Data Types {Lecture}
▪ Type Casting {Lecture}
▪ Arrays and Strings {Lecture}
▪ SystemVerilog Building Blocks {Lecture}
▪ Structures {Lecture, Lab}
▪ Unions {Lecture, Lab}
▪ Additional Operators in SystemVerilog {Lecture}
Day 2
▪ Procedural Statements {Lecture, Lab}
▪ Control Flow Statements {Lecture}
▪ Functions {Lecture}
▪ Tasks {Lecture}
▪ Packages {Lecture, Lab}
▪ Interfaces {Lecture}
Day 3
▪ Introduction to SystemVerilog for Verification
▪ Data Types
▪ Tasks and Functions
▪ Lab 1: Implementing Tasks and Functions
▪ SystemVerilog Verification Building Blocks
▪ Lab 2: Connecting the Testbench to the DUT
▪ Object-Oriented Modeling
▪ Lab 3: Object-Oriented Modeling
▪ Randomization
▪ Lab 4: Randomization
▪ Coverage
▪ Lab 5: Coverage
▪ Assertions
▪ Lab 6: Assertions
▪ Direct Programming Interface
▪ Demo: Direct Programming Interface
▪ Inter Process Communication
Topic Descriptions