Price 4585 + VAT /15 Tcs
DURATION 6 Half Days

Course Overview

This course will update experienced ISE® software users to utilize the Vivado® Design Suite. Learn the underlying database and static timing analysis (STA) mechanisms. Utilize Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports. Learn to make appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces for your FPGA design.
You will also learn the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an FPGA design methodology case study. The UltraFast Design Methodology Checklist is also introduced.

Level:

FPGA 2

Who should attend?

Existing Xilinx ISE Design Suite FPGA designers

Prerequisite:

FPGA design experience

  • Completion of the Essentials of FPGA Design, Designing for Performance, or Advanced FPGA Implementation courses or equivalent knowledge of Xilinx ISE software implementation tools, techniques, architecture, and FPGA design techniques. Completion of the Vivado Design Suite for ISE Project Navigator Users course is strongly recommended.
  • Intermediate VHDL or Verilog knowledge

 

Software Tools:

Vivado System Edition 2013.3

Hardware:

Architecture: 7 series FPGAs*

  • Demo board: None*

 

Skills Gained: After completing this training, you will be able to:

  • Access primary objects from the design database and filter lists of objects using properties
  • Describe setup and hold checks and describe the components of a timing report
  • Create appropriate input and output delay constraints and describe timing reports that involve input and output paths
  • Explain the impact that manufacturing process variations have on timing analysis and describe how min/max timing analysis information is conveyed in a timing report
  • Describe all of the options available with the report_timing and report_timing_summary commands
  • Describe the timing constraints required to constrain system-synchronous and source-synchronous interfaces
  • Analyze a timing report to identify how to center the clock in the data eye
  • Create scripts for the project-based and non-project batch design flows
  • Describe the Vivado Design Suite FPGA Design Methodology Checklist
  • Identify key areas to optimize your design to meet your design goals and performance objectives
  • Define a properly constrained design
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
  • Build resets into your system for optimum reliability and design speed
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
  • Identify timing closure techniques using the Vivado Design Suite
  • Describe how the Xilinx design methodology techniques work effectively through case study/lab experience

 

Lab Description:

Lab DescriptionLab 1: Vivado IDE Database ndash; Utilize the Vivado IDE database to set properties on a design.
Lab 2: Vivado IDE Clocks ndash; Create complete XDC constraints for the clocking resources in a design. Implement the design and use the available clocking reports to verify results. Understand the first step in the Xilinx baselining recommendation.
Lab 3: I/O Constraints ndash; Create input and output constraints for a source-synchronous design by using the Timing Constraints utility. You will also generate useful timing reports to verify the timing results. Understand the second step in the baselining recommendation.
Lab 4: Timing Exceptions ndash; Use the Timing Constraints window to enter timing exceptions in the XDC format. You will also generate a useful timing report to verify the timing results. Understand the third and last step in the baselining recommendation.
Lab 5: Advanced I/O Timing ndash; Make I/O timing constraints for a source-synchronous, double data rate (DDR) interface. Perform a static timing analysis of the interfaces to determine the optimal clock and data relationship for maximum setup and hold-time margin. Finally, adjust the data path delay to realize the optimal timing solution.
Lab 6a: Scripting in the Project-Based Flow ndash; Write Tcl commands in the project-based flow for the design process (from creating a new project through implementation).
Lab 6b: Scripting in the Non-Project Batch Flow ndash; Write Tcl commands in the non-project batch flow for the design process (from creating a new project through implementation).
Lab 7: Resets ndash; Investigate the proper design and use of resets. Examine the impact of seeing a design built originally with asynchronous resets, having resets removed, and finally with synchronous resets only used where necessary.
Lab 8: SRL and DSP Inference ndash; Evaluate the implementation results of a design that uses asynchronous resets and infers more dedicated hardware resources when resets are selectively removed from the design. You will also learn how to infer the DSP hardware resources for other common functions required by most FPGA designs.
Lab 9: Timing Closure and Design Conversion ndash; Learn how a generic processor design was optimized for the 7 series device architecture with basic design changes that impacted the dedicated hardware usage, design speed, and the device utilization.

Recommended RELs

Essential Tcl Scripting for the Vivado Design Suite course

  • Vivado Design Suite for ISE Software Project Navigator Users course

 

Course Outline:

Session 1

1. Design Methodology Summary
2. Vivado IDE Review
3. Accessing the Design Database
Lab 1: Vivado IDE Database

Session 2

4. Static Timing Analysis and Clocks
Lab 2:
Vivado IDE Clocks
5. Inputs and Outputs
Lab 3:
I/O Constraints

Session 3

6. Timing Exceptions
Lab 4:
Timing Exceptions
7. Advanced Timing Analysis
8. Advanced I/O Interface Constraints
Lab 5:
Advanced I/O Timing

Session 4

9. Project-Based and Non-Project Batch Design Flows
Scripting Using Project-Based and Non-Project Batch Flows
Lab 6a:
Scripting in the Project-Based Flow
Lab 6b: Scripting in the Non-Project Batch Flow
10. UltraFast Design Methodology Checklist

Session 5 

11. FPGA Design Methodology
12. HDL Coding Techniques
13. Reset Methodology
Lab 5:
Resets
Lab 6: SRL and DSP Inference

Session 6

14. Synchronization Circuits and the Clock Interaction 15. Report
16. Timing Closure
FPGA Design Methodology Case Study
Lab 7:
Timing Closure and Design Conversion
Appendix: Timing Constraints Review
Appendix: Synchronization Circuits and the Clock Interaction Report
Appendix: Fanout and Logic Replication
Appendix: Pipelining lab

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