This course offers introductory training on the Vivado Design Suite. This course is for experienced ISE software users who want to take full advantage of the Vivado Design Suite feature set. Learn about the Vivado Design Suite projects, design flow, Xilinx design constraints, and basic timing reports.
Who should attend?Existing Xilinx ISE® software Project Navigator FPGA designers
• Basic knowledge of the VHDL or Verilog language
• Digital design knowledge
Vivado System Edition 2017.3
• Architecture: UltraScale™ and 7 series FPGAs*
• Demo board (optional): Kintex® UltraScale FPGA KCU105 evaluation board or Kintex-7 FPGA KC705 board*
Skills Gained: After completing this training, you will be able to:
• Use the Project Manager in the Vivado Design Suite to start a new project
• Identify the available Vivado IDE design flows (project based and non-project batch)
• Identify file sets (HDL, XDC, simulation) and analyze designs using the cross-selection capabilities, Schematic viewer, and
• Synthesize and implement an HDL design
• Apply HDL coding techniques and reset methodology to your design
• Utilize a systematic approach to apply synchronous design techniques
• Use the Vivado IP flow to add and customize IPs
• Explain how to use Tcl commands and scripts in your design
• Write Tcl scripts in Vivado Design Suite project and non-project modes
Lab Description:1. Vivado Design Suite Project Mode
Create a project, add files to the project, explore the Vivado IDE, and simulate the design.
2. Synthesis and Implementation
Create timing constraints according to the design scenario and synthesize and implement the design.
3. Basic Design Analysis in the Vivado IDE
Use the various design analysis features in the Vivado Design Suite.
4. Vivado Design Suite I/O Pin Planning
Use the I/O Pin Planning layout to perform pin assignments in a design.
Investigates the impact of using asynchronous resets in a design.
6. Register Duplication
Use register duplication to reduce high fanout nets in a design.
7. Vivado IP Flow
Customize IP, instantiate IP, and verify the hierarchy of your design IP.
8. Designing with the IP Integrator
Use the Vivado IP integrator to create the uart_led subsystem.
9. Introduction to the Tcl Environment
Introduces Tcl (tool command language).
10. Design Analysis Using Tcl Commands
Analyze a design using Tcl commands.
11. Scripting in Vivado Design Suite Project Mode
Explains how to write Tcl commands in the project-based flow for a design.
12. Scripting in Vivado Design Suite Non-Project Mode
Write Tcl commands in the non-project batch flow for a design.
1. Introduction to the Vivado Design Suite
Introduces the Vivado Design Suite.
2. Introduction to Vivado Design Flows
Introduces the Vivado design flows: the project flow and non-project batch flow.
3. Vivado Design Suite Project Mode
4. Behavioral Simulation
Performs behavioral simulation for your design.
5. Synthesis and Implementation
6. Basic Design Analysis in the Vivado IDE
7. Vivado Design Suite I/O Pin Planning
8. Xilinx Power Estimator Spreadsheet
Estimate the amount of resources and default activity rates for a design and evaluate the estimated power calculated by XPE.
9. UltraFast Design Methodology: Board and Device Planning
Introduces the methodology guidelines covered in this course and the UltraFast Design Methodology checklist.
10. HDL Coding Techniques
Covers basic digital coding guidelines used in an FPGA design.
12. Synchronous Design Techniques
Introduces synchronous design techniques used in an FPGA design.
13. Vivado IP Flow
14. Designing with the IP Integrator
15. UltraFast Design Methodology: Design Creation
Overview of the methodology guidelines covered in this course.
16. Vivado Design Suite Non-Project Mode
Create a design in the Vivado Design Suite non-project mode.
17. Introduction to the Tcl Environment
18. Design Analysis Using Tcl Commands
19. Scripting in Vivado Design Suite Project Mode
20. Scripting in Vivado Design Suite Non-Project Mode