The hands-on labs provide students the experience of designing, expanding, and debugging an embedded system, creating and importing a custom AXI4 peripheral, and performing bus functional model simulation.
Who should attend?Engineers who are interested in developing embedded systems with the Xilinx Zynq All Programmable SoC processor core using the Vivado IP integrator.
• FPGA design experience
• Completion of the Essentials of FPGA Design course or equivalent knowledge of Xilinx Vivado software implementation tools
• Basic understanding of C programming
• Basic understanding of microprocessors
• Some HDL modeling experience
• Vivado Design or System Edition 2015.1
• Architecture: Zynq-7000 All Programmable SoC and 7 series FPGAs*
• Demo board: Zynq-7000 All Programmable SoC ZedBoard*
Skills Gained: After completing this training, you will be able to:
• Describe the various tools that encompass a Xilinx embedded design
• Rapidly architect an embedded system containing a Cortex™-A9 processor by using the Vivado IP Integrator and Customization Wizard
• Develop software applications utilizing the Eclipse-based Software Development Kit (SDK)
• Apply debugging techniques, including the use of the Vivado logic analyzer tool for cross triggering an embedded system
• Create, import, and integrate a custom AXI4 peripheral to an embedded system in the Vivado Design Suite
• Perform bus functional model (BFM) simulation using AXI and Zynq AP SoC BFM cores
Lab 1: Building a Basic Zynq AP SoC Design –Create a project using the IP integrator to develop a basic hardware system and generate a series of netlists for the embedded design. Complete the processes using the SDK tools to create a software BSP and sample application. Configure the device and download the application.
Lab 2: Debugging on the Zynq AP SoC – Evaluate debugging the hardware and software components of a Zynq All Programmable SoC design.
Lab 3: Integrating Custom IP with the Zynq AP SoC – Connect a programmable logic (PL) design to the embedded processing system (PS).
Lab 4: Using the Zynq AP SoC BFM for System Simulation – Test an embedded system through a bus functional model simulation using AXI and Zynq AP SoC BFM cores.
1. Smarter Systems Workshop Overview
2. Lab 1: Building a Basic Zynq AP SoC Design
3. Verification and Debug of a Zynq AP SoC Design
4. Lab 2: Debugging on the Zynq AP SoC
5. Designing a Custom Peripheral
6. Lab 3: Integrating Custom IP with the Zynq AP SoC
7. Zynq AP SoC: Verification and Performance
8. Lab 4: Using the Zynq AP SoC BFM for System Simulation