This course is structured to provide hardware designers with an overview of many of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.
Level:Embedded Hardware 3
Who should attend?Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ MPSoC device.
• Suggested: Understanding of the Zynq-7000 architecture
• Basic familiarity with embedded software development using C (to support testing of specific architectural elements)
• Vivado® Design Suite 2019.1
• Hardware emulation environment:
• Ubuntu desktop
• Host computer for running the above software*
Skills Gained: After completing this training, you will be able to:
• Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
• List the various power domains and how they are controlled
• Describe the connectivity between the processing system (PS) and programmable logic (PL)
• Utilize QEMU to emulate hardware behavior
Lab DescriptionZynq UltraScale+ MPSoC Application Processing Unit
Introduction to the members of the APU, specifically the Cortex™-A53 processor and how the cluster is configured and managed.
Zynq UltraScale+ MPSoC HW-SW Virtualization
Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used.
Zynq UltraScale+ MPSoC Real-Time Processing Unit
Introduction to the various elements within the RPU and different modes of configuration.
Zynq UltraScale+ MPSoC Booting
How to implement the embedded system, including the boot process and boot image creation.
Understanding how the PS and PL connect enables designers to create more efficient systems.
Zynq UltraScale+ MPSoC PMU
Overview of the PMU and the power-saving features of the device.
1. Zynq UltraScale+ MPSoC Application Processing Unit
2. Zynq UltraScale+ MPSoC HW-SW Virtualization
3. Zynq UltraScale+ MPSoC Real-Time Processing Unit
5. Zynq UltraScale+ MPSoC Booting
6. Zynq UltraScale+ MPSoC System Protection
7. Zynq UltraScale+ MPSoC Clocks and Resets
9. Zynq UltraScale+ MPSoC PMU