Date 12-13.08.2019
Price 3145 + VAT /10 Tcs
DURATION 2 Days

Course Overview

This one-day course is structured to provide hardware designers with an overview of many of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.

Level:

Embedded Hardware 3

Who should attend?

Hardware designers interested in understanding the architecture and capabilities of the Zynq UltraScale+ MPSoC device.

Prerequisite:

• Suggested: Understanding of the Zynq-7000 architecture
• Basic familiarity with embedded software development using C (to support testing of specific architectural elements)

Software Tools:

• Vivado® Design Suite 2017.3

• May require special Zynq UltraScale+ MPSoC family license

• Hardware emulation environment:

• VirtualBox
• QEMU
• Ubuntu desktop
• PetaLinux

Hardware:

• Host computer for running the above software*
* This course focuses on the Zynq UltraScale+ MPSoC architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab environment or other customizations. This version of the class does not use a physical board, but rather a local emulation environment and the Vivado Design Suite.

Skills Gained: After completing this training, you will be able to:

• Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
• List the various power domains and how they are controlled
• Describe the connectivity between the processing system (PS) and programmable logic (PL)
• Utilize QEMU to emulate hardware behavior

Lab Description:

Zynq UltraScale+ MPSoC Application Processing Unit
Introduction to the members of the APU, specifically the Cortex™-A53 processor and how the cluster is configured and managed.
Zynq UltraScale+ MPSoC HW-SW Virtualization
Covers the hardware and software elements of virtualization. The lab demonstrates how hypervisors can be used.
Zynq UltraScale+ MPSoC Real-Time Processing Unit
Introduction to the various elements within the RPU and different modes of configuration
Zynq UltraScale+ MPSoC Booting
How to implement the embedded system, including the boot process and boot image creation.
AXI
Understanding how the PS and PL connect enables designers to create more efficient systems.
Zynq UltraScale+ MPSoC PMU
Overview of the PMU and the power-saving features of the device.

Course Outline:

1. Zynq UltraScale+ MPSoC Application Processing Unit

2. Zynq UltraScale+ MPSoC HW-SW Virtualization

3. Zynq UltraScale+ MPSoC Real-Time Processing Unit

4. QEMU
Introduction to the Quick Emulator, which is the tool used to run software for the Zynq UltraScale+ MPSoC device when hardware is not available.

5. Zynq UltraScale+ MPSoC Booting

6. Zynq UltraScale+ MPSoC System Protection
Covers all the hardware elements that support the separation of software domains.

7. Zynq UltraScale+ MPSoC Clocks and Resets
Overview of clocking and reset, focusing more on capabilities than specific implementations.

8. AXI

9. Zynq UltraScale+ MPSoC PMU

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