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- SystemVerilog for Design and Verification Duration: 8 Half daysDate: 18/10/2020
- Doulos UVM Adopter Class Duration: 6 Half daysDate: 22/11/2020
- Comprehensive SystemVerilog Duration: 5 Days
- VHDL – For Designers Duration: 4 Days
- SystemVerilog for Verification Specialists Duration: 4 Days
- Doulos OVM Adopter Class Duration: 4 Days
- VHDL – Doulos Expert for Design and Verification Duration: 3 Days
- VHDL – Expert VHDL for Design and Verification Duration: 3 Days
- Doulos Advanced Design with VHDL Duration: 2 Days
- VMM Adopter Class Duration: 2 Days
- SystemVerilog for FPGA/ASIC Design Duration: 4 Days
- Doulos SystemVerilog for Designers Duration: 3 Days
