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- SystemVerilog for Design and Verification Duration: 8 Half daysDate: 17,18,24,25/01/2021
- Doulos UVM Adopter Class Duration: 6 Half daysDate: 14,18,21,25/04/2021
- Comprehensive SystemVerilog Duration: 5 Days
- VHDL – For Designers Duration: 4 Days
- SystemVerilog for Verification Specialists Duration: 4 Days
- Doulos OVM Adopter Class Duration: 4 Days
- VHDL – Doulos Expert for Design and Verification Duration: 3 Days Date: 14,15,16/03/2021
- VHDL – Expert VHDL for Design and Verification Duration: 3 Days Date: 14,15,16/03/2021
- Doulos Advanced Design with VHDL Duration: 2 Days Date: 7,8/03/2021
- VMM Adopter Class Duration: 2 Days
- SystemVerilog for FPGA/ASIC Design Duration: 4 Days
- Doulos SystemVerilog for Designers Duration: 3 Days
