Comprehensive PCI Express 5.0
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Price 10,290 ILS
/ 30 Tcs
DURATION 5 Days
Skills Gained: After completing this training, you will be able to:
- Fundamentals of the PCIe technology and PCI-SIG Spec key features
- Deep dive into the protocol specification for each PCI Express Layer
- PCI Express Software and Configuration
- Power Management and Error Handling protocols
- PCIe advanced features added to the Gen3 – Gen5 specifications
- Real platform’s Configuration space registers analyzes
Course Outline:
Introduction to PCI Express
- PCI express as PCI/PCI-X evolution
- PCIe System overview (topology, type of devices and traffic types)
- CFG space: Header 0/1 and list of capabilities
- PCI Express layers architecture
- Transactions types
- PCI Express System characteristics
- PCIe link performance: Protocol overhead, Outstanding Reads/MPS effect
Software model
- Configuration space
- PCI-compatible Type 0/Type 1 Headers and Capabilities
- PCI Express Extended Capabilities (Gen1-> Gen5)
- Configuration space access mechanism (Legacy/ECAM)
- Bus numbering and ID routing
- Memory and /IO spaces
- Memory space concepts
- BARs and Base/Limit registers initialization
- Resizable BARs
- Interrupts
- MSI and MSI-X
- INTx emulation in PCI Express
- PCI Express enumeration
- BIOS enumeration and resource allocation
Transaction Layer
- Packet types
- TLP header fields
- Transaction flows, 10 bit Tag
- Quality of Service
- Transaction’s ordering
- Consumer Producer mode
- PCI Express Ordering Table
- Relaxed ordering
Flow Control (Data Link Layer)
- Overview, transmit credit principle
- Related counters
- Credit update frequency
- Scaled Flow Control and Data Link Feature Exchange
ACK / NAK Protocol (Data Link Layer)
- Acknowledgement objectives
- Counters /timers in the transmitter and the receiver
- ACK/NACK Sequences
- Protocol analyzer examples – ACK/NACK and FC
Physical and Electrical Layers
- Physical Layer (Gen1 and Gen2)
- 8-bit / 10-bit coding and Scrambling
- Ordered sets
- Byte stripping
- Physical Layer (Gen3-5)
- Ordered Set Blocks and Data Blocks
- Packet Framing in Data Streams
- Control SkpOS format and usage
- Physical Layer Electrical (Gen1-5)
- PCIe channel
- Clock schemes, SSC and SRIS , elastic buffer operation
- Gen2 De-emphasis
- Gen3/4 Equalization
- PCI Express Retimers
- Lane Margining at Receiver (Gen4-5)
Clocks and System Resets
- PCIe clock schemes (Common SSC / SRIS)
- PCIe Reset Mechanisms: Cold, Warm and Hot Reset
- Function Level Reset (FLR)
Link Initialization and Training (LTSSM)
- Link Up flow:
- Detect, Polling, Configuration, L0 States
- Recovery state and Speed Change
- Link Width change
- Equalization Training flow, TSEQ fields
- Hot Reset, Disable and Loopback states
Power Management
- PCI express device power states overview
- Enter and exit of power states
- Link Power States
- Power management packets and messages
- Active State Power Management (ASPM)
- PME/Wake/Beacon support
Error Management
- General principles
- PCI-like error management
- PCI Express basic error management
- PCI Express Advanced Error Reporting (AER)