ARM – CORTEX-A15 / CORTEX-A7 BIG/Little Implementation

Course Outline:

First day

OVERVIEW OF CORTEX-A15MP AND CORTEX-A7 [1-hour]
• Cortex-A15 & Cortex-A7 architecture
• AMBA4 coherent interconnect capabilities
• Inner Shareable vs Outer Shareable attribute
• I/O MMU
• 64-Byte cacheline size, integrated L2 cache
• VFPv4 and SIMDv2
• Supported instruction sets, new integer divide instructions
• Highlighting differences between Cortex-A7 and Cortex-A15
• Configurable options

INSTRUCTION PIPELINE [1-hour]
• Global organization, triple issue capability for Cortex-A5
• Single issue capability for Cortex-A7
• Fetch / decode / rename / dispatch stages
• Loop mode
• Branch accelerators: Branch Target Buffer, Global History Buffer, Return Stack, Indirect predictor
• 2-level dynamic predictor
• Branch prediction maintenance operations

INTRODUCTION TO HYPERVISOR STATE [1-hour]
• Processor privilege levels state machine, user, guest OS, hypervisor
• Detailing the various operation modes (Bare-Metal, Hypervisor kernel and user task, Hypervisor with Guest partition)
• Asymmetric approach, no support for Virtualization of Secure state functionality
• SVC, HVC and SMC instructions
• Objective of the Hypervisor: virtualizing the hardware platform on which the guest partition is executed
• Hypervisor related instructions and registers
• Support for interrupt nesting in Hypervisor mode
• LR banking disabling when running in hypervisor mode
• List of registers that have to be saved / restored to be able to suspend / resume a guest partition
• Accessing banked registers or any Non-Secure mode while running in Hypervisor mode
• Detecting VFP/Neon utilization by a Guest partition

EXCEPTION MECHANISM [2-hour]
• Hypervisor vector table
• Utilization of Vector #5 to trap Guest partition events
• System Call into Hypervisor mode
• Asynchronous exceptions
• Virtual Interrupt and Abort bits control, IRQ, FIQ, external abort routing control
• Hypervisor exception return
• Use of Hypervisor mode in Secure State
• Taking exceptions into Hypervisor mode
• Simplifying the design of the Guest partition trap handler by using the HSR register

GENERIC INTERRUPT CONTROLLER (GICv2) [3-hour]
• Integration in a SoC based on Cortex-A15MP and Cortex-A7MP
• Highlighting the new features with regard to Cortex-A9MP, especially hypervisor related interrupts
• Steering interrupts to guest OS or Hypervisor
• Virtual CPU interface
• Split EOI functionality
• Deactivating an interrupt source from the Virtual CPU interface
• Front-end interface accessed by the Guest Kernel
• Back-end interface accessed by the Hypervisor
• Writeable Active Bits

Second day

AMBA4 [3-hour]
• AXI-4
– Burst greater than 16 beats
– Quality of Service signaling
– Multiple region interfaces
– Restrictions for Non-modifiable and Modifiable transactions
– Updated meaning of Read Allocate and Write Allocate
– Memory type requirements
– Transaction buffering
• AXI-4 stream protocol
– Byte types, data, position, null
– Byte stream
– Sparse stream
– Data merging, packing, and width conversion
– Packet boundaries
– User sideband signaling
• AXI-4 lite
– Burst length of 1
– all accesses are equivalent to AWCACHE or ARCACHE equal to b0000
– No exclusive access support
• AXI Coherency Extension (ACE)
– Shareability domains
– Coherency model, cache states
– Additional channel signals
– New channels, snoop address, snoop response, snoop data
– Studying through sequences how a load request and a store request will be handled whenever they are marked as outer shareable requests
– Distinguishing partial cacheline writes from entire cacheline writes
– Using ReadUnique, CleanUnique and MakeUnique requests
– Distributed Virtual Memory (DVM)
– DVM synchronization message
– Selecting the coherency state machine: MESI or MOESI according to the capabilities of the interconnect
– Snoop filtering
– Broadcast interface
• Exported barriers
– DMB / DSB inner shareable, outer shareable or system
– Explaining through use cases the purpose of these 3 kinds of barriers

HARDWARE IMPLEMENTATION OF CORTEX-A15 AND CORTEX-A7 [1-hour]
• Clock domains, CLK, PCLKDBG, ACLKM, ACLKS, ATCLK, PERIPHCLK
• Clock gating, related CP15 registers
• Resets, power-on reset timing diagram
• Valid reset combinations
• Power domains, cluster power gating
• Power-on reset sequence, soft reset sequence
• Automatic L1 caches invalidation
• L2 cache invalidation, using L2RESETDISABLE
• Power management, WFI / WFE, dormant mode based on L2 memory
• Maintaining coherency while CPUs are in standby state
• Interface to the Power Management Unit
• Powering down a CPU
• External debug over power down
• Neon and VFP clock gating

CCI-400 CACHE COHERENT INTERCONNECT [2-hour]
• AMBA 4 snoop request transport
• Snoop connectivity and control
• ACE master interface
• ACP slave interface
• Connecting 2 CPUs through CCI, managing coherency domains