ARM CORTEX-R52
Start Date: Please contact us
Course Overview
This course aims to explain the architecture of the ARM Cortex-R52 to enable participants to efficiently design a SoC based on this CPU and develop low level software. Attendees will get a detailed understanding of the internal architecture, especially the implementation of the V8-R specification. They will study the mechanisms specific to ARM V8-R processors, particularly caches, TCMs and MPU. Labs contribute to become familiar with V8-R programming.
Who should attend?
Engineers and technicians who develop SoCs and systems based on the ARM Cortex-R52 architecturePrerequisite:
• Basic knowledge of a CPU or DSP
• See courses ARM_AXI, ARM_NEON and ARM_CRS (CoreSight)
Course Family
ARMv8-R Cortex-R CPU
Course Outline:
DAY 1
1. ARM BASICS (2-hours)
Modes and states
Exception mechanism, vector table
AAPCS
Cortex profiles
2. CORTEX-R52 ARCHITECTURE (2-hours)
Instruction pipeline
CPU internal data and instruction paths
Master ports: AXIM, Flash and LLPP
AXI slave interface
Configurable options
Architecture of a SoC based on Cortex-R52
Highlighting the differences with regard to Cortex-R8
3. INTRODUCTION TO VIRTUALIZATION (2–hour)
Objectives, isolating the partition from the hardware
Types of virtualization: para-virtualization and full virtualization
Enabling direct access to I/Os from guest OS
Hypervisor operation, 2-stage address translation
ARM V8-A hypervisor in Non Secure side
Enabling traps to hypervisor when a guest OS attempts to access a physical resource
Converting physical interrupts into virtual interrupts
4. V8-R VIRTUALIZATION EXTENSIONS (1-hour)
Support for AArch32 Execution state
Support for Exception levels, EL0, EL1, and EL2
New hypervisor privilege level
Re-entrant mode
Hypervisor exception management, trapping
Target exception level definition
Fast interrupts
DAY 2
5. HARDWARE IMPLEMENTATION (1-hour)
Reset, booting from TCM
Booting into EL1
Clocking
Power management, P-channel interfaces
Power gating, power domains
AXIM interface, AXIM data prefetchers
Low-latency peripheral port, LLPP AXI transfer restrictions
Flash interface
AXIS interface
6. SAFETY FEATURES (1-hour)
Dual-Core Lock-Step (DCLS) operation
Split/Lock configuration
Memory Reconstruction Port
Protection of internal memory through ECC
ECC on AXI bus
Flash interface ECC scheme
Error injection
Bus timeout
Soft error status registers
7. INSTRUCTION PIPELINE (1-hour)
Pipeline stages
Superscalar implementation
Branch accelerators
Branch predictor maintenance instructions
In order execution
8. GICv3 (3-hours)
Distributor, Redistributors and CPU interfaces
GICv3, SPIs, PPIs and SGIs
Requirements to implement nesting
Interrupt latency
Priority management, nesting
Software generated interrupts
Low power modes, wake up conditions
Converting a physical interrupt request into a virtual interrupt request
Svc exception management is explained through a lab
A GIC handler is studied in a lab
9. GENERIC TIMER (1-hour)
System counter
Distributing the System Counter value
Physical vs virtual time
Timers
Event stream
DAY 3
10. PAGE ATTRIBUTES (1-hour)
Explaining the differences between Normal and Device types
Bufferability
Speculative loads
Store merging
New V8-R attributes
Data and instruction barriers, new DFB instruction
Self-modifying code
11. MEMORY PROTECTION UNIT (1-hour)
Objectives of the MPU
ARMv8-R Protected Memory System Architecture
EL2- and EL1-controlled MPUs
PMSAv8-32 memory access permission and attribute control
Combining EL2 and EL1 attributes
Default memory maps and Background region checks
Initializing the MPU
A lab explains how to initialize the MPU and also provides an example of Data Abort handler
12. SYSTEM MMU, MMU500 (1-hour)
Objectives
TCU and TBUs
Associating a table of descriptor with a master request, stream ID
TLB, tablewalk caches
Fault detection and report
Distributed Virtual Memory
13. CACHES AND TCMS (2-hours)
Cache basics
Cortex-R52 L1 subsystem
Error detection, parity, ECC, soft error fault management
L1 caches Write-Through behavior, store buffers
Cache prefetch
Cache maintenance instructions
Self-modifying code
Segregation of instruction and data cache ways between Flash and AXIM
Data coherency when data buffers are shared by CPU and DMA
TCMs, base address configuration
TCM testing using the MBIST interface
14. EXCLUSIVE RESOURCE MANAGEMENT (2-hour)
Single-processor / multi-task RTOS, local monitor
Multiple-processor / multi-task RTOS, local and global monitors
Spin lock sequence
Using events
DAY 4
15. CORESIGHT DEBUG (2-hours)
Invasive debug, breakpoint, watchpoint, event catch
Non-invasive debug, PC sampling, ETM, performance monitoring
Cross-Triggering Interface
ROM table
Debug Communication Channel
Semi-hosting
Cache dump
Debug over power down
Process ID and VM ID change tracing
16. V8-R INSTRUCTION SET SUMMARY (2-hours)
Direct and indirect branches
B-operand capabilities, immediate value, shifting
Literal pool
Arithmetic and logical operations
Addressing modes, load / store and load / store multiple instructions
Stack management
SIMD instructions
Many labs help to understand how to become familiar with assembler programming
17. FLOATING-POINT UNIT (1-hour)
Floating-point number coding, IEEE754
Floating-point arithmetic
Exceptions, handling underflow, overflow, invalid result and inexact result events
Flush-to-zero and default NaN modes
18. EMBEDDED SOFTWARE DEVELOPMENT (2-hours)
The code generation flow
Compiler hints and tips, coding guidelines based on AAPCS
GCC linker command file, syntax
Placing the vector table
Long branch veneers
Using overlays
Performance issues when declaring public discrete global variables
Many labs help to understand how to customize a linker command file
Compiler hints and tips are also studied through labs
