The process of ASIC design and production becomes more and more expensive.
NRE may be millions of $$. Time to market is always critical and cycle needed to be shorter.
Although good verification environment is essential for ASIC success, it may not be enough.
Due to very long simulation cycle times , lack of manpower , timing issues , uncovered system scenarios , lack of software drivers etc.
ASIC prototyping in FPGA increases significantly the probability of ASIC 1st time pass.
However, there are technology differences between ASIC and FPGA that should be taken into consideration. This course will emphasize the differences and how they should be handled
Who should attend?VLSI/ASIC team leader/project manager
Experience in RTL design
- Knowledge in Xilinx FPGA tools (only for 2nd day)
ISE (for the 2nd day)
Skills Gained: After completing this training, you will be able to:
- Techniques for RTL design that fits code to FPGA and ASIC
- Understand the limitations of the prototyping process
- Understand the cost of prototyping process
- Tips to fasten synthesis and place/route cycles
Verilog with references to VHDL
Background and explanations
1. Typical ASIC development process with and without FPGA
2. Benefits from adding FPGA to the verification process
3. Handling 3rd parties IP’S
5. System aspects FPGA vs. ASIC
6. Design partitioning
7. Timing issues
Xilinx Specific with Labs
Lab 1: Clocking – In this lab we will understand the ASIC clock tree vs. FPGA clock tree. What may be identical and where are the differences.
Lab 2: Memory instantiation – In this lab we will show how to instantiate memories. ROM, RAM and special ASIC memories.
Lab 3: I/O pad – We will focus on the differences between ASIC and FPGA I/O pads. Coding Style to improve I/O performance.
Lab 4: Production test modes in ASIC – Usually in ASIC there are special functions for testing. We will show how these functions can be handles in FPGA.
Lab 5: Power and analog IP’S in ASIC – If our ASIC contains analog IP’S or power units, we have to handle them in FPGA.
Lab 6: Fastening compilation duration – Synthesis and place / route may be very long cycles. We will learn how to shorten these cycles.