Price 3145 + VAT /10 Tcs
DURATION 2 Days

Course Overview

This course introduces the Xilinx Agile Mixed Signal (AMS) solution and the appropriate tools and techniques for hardware engineers and analog engineers to utilize this solution. The complete front-to-back design flow is covered, including the evaluation of the Xilinx Analog-to-Digital Converter (XADC) block utilizing the KC705 board and the evaluator add-on card, the various ways to include the XADC in your design, XADC simulation of an analog input, viewing the digital output, and implementation. Additionally, labs are provided that support each topic, including the compete flow.

Level:

FPGA 3

Who should attend?

Hardware and analog designers who want to maximize utilization of the Xilinx AMS solution.

Prerequisite:

  • Essentials of FPGA Design
  • Basic VHDL or Verilog programming knowledge
  • C programming knowledge recommended
  • Experience with the Xilinx ISE and Embedded Development Kit (EDK) software tools

 

Software Tools:

• Xilinx ISE® Design Suite: System Edition 14.3

Hardware:

  • Architecture: Xilinx 7 series FPGAs
  • Demo boards: Kintex™-7 KC705 board and AMS evaluator card

 

Skills Gained: After completing this training, you will be able to:

  • Describe the basics of analog-to-digital converters (ADC)
  • Describe the benefits of having a flexible analog interface (the XADC block) coupled with the programmable logic capability of 7 series FPGAs and the Zynq™-7000 Extensible Processing Platform (EPP)
  • List the key specifications for the Xilinx Analog-to-Digital Converter block
  • Identify the different flows for evaluating and adding the XADC core into your design using the ISE Design Suite tools

 

Lab Description:

Lab 1: Evaluating the XADC Block – Use the AMS TRD to evaluate the XADC performance, configure the XADC settings and view the sampled data using the Lab View GUI environment.

Lab 2: AMS HDL State Machine Control and Simulation – Use the XADC wizard to generate an XADC core, instantiate the XADC core to a RTL project, and simulate and implement the design.

Lab 3: EDK Design Flow – Use the EDK IP Catalog to add the XADC AXI IP core to the design, implement the design, and run a test application utilizing the XADC core

Course Outline:

1. AMS Overview

2. ADC Theory

3. XADC Architecture

4. AMS Design Flow

5. XADC Debug and Monitor

Lab 1: Evaluating the XADC Block
HDL Design Flow

Lab 2: AMS HDL State Machine Control and Simulation
EDK Design Flow

Lab 3: EDK Design Flow
Course Summary

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