Designing with UltraScale FPGA Transceivers

Start Date: 11/04/2022

Price 4,228 ILS

/ 12 Tcs

DURATION 2 Days

Course Overview

Learn how to employ serial transceivers in your UltraScale™ FPGA design. Understand and utilize the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the UltraScale FPGAs Transceiver Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.

Level:

Connectivity 3

Who should attend?

FPGA designers and logic designers

Prerequisite:

• Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
• Familiarity with logic design (state machines and synchronous design)
• Basic knowledge of FPGA architecture and Xilinx implementation tools are helpful
• Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

Software Tools:

• Vivado® System Edition 2014.4
• Mentor Graphics ModelSim simulator 10.4

Hardware:

• Architecture: UltraScale FPGAs*
• Demo board: None*

Skills Gained: After completing this training, you will be able to:

• Describe and utilize the ports and attributes of the serial transceiver in UltraScale FPGAs
• Effectively utilize the following features of the gigabit transceivers:

• 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding

• Pre-emphasis and linear equalization

• Use the UltraScale FPGAs Transceivers Wizard to instantiate GT primitives in a design
• Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design

Lab Description:

Lab 1: Transceiver Core Generation – Use the UltraScale FPGAs Transceivers Wizard to create instantiation templates.
Lab 2: Transceiver Simulation – Simulate the transceiver IP by using the IP example design.
Lab 3: 64B/66B Encoding – Generate a 64B/66B transceiver core by using the UltraScale FPGAs Transceivers Wizard, simulate the design, and analyze the results.
Lab 4: Transceiver Implementation – Implement the transceiver IP by using the IP example design.

Course Outline:

1. UltraScale FPGA Overview
2. UltraScale FPGA Transceivers Overview
3. UltraScale FPGAs Transceivers Clocking and Resets
4. Transceiver Wizard Overview
Lab 1: Transceiver Core Generation
5. Transceiver Simulation
Lab 2: Transceiver Simulation
6. PCS Layer General Functionality
7. PCS Layer Encoding
Lab 3: 64B/66B Encoding
8. Transceiver Implementation
Lab 4: Transceiver Implementation
9. PMA Layer Details
10. Transceiver Board Design Considerations
11. Signal Integrity for Transceiver Designs
12.Transceiver Test and Debugging
13. Transceiver Application Examples