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Start Date: 22/05/2023
Price 4,228 ILS
/ 12 Tcs
DURATION 2 Days
Course Overview
In this two-day course, you will learn how to employ serial transceivers in your 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.
Additional topics include use of the Transceivers Wizards, synthesis and implementation considerations, board design as it relates to the transceivers, and testing and debugging. This course combines lectures with practical hands-on labs.
Level:
Connectivity 3Who should attend?
FPGA designers and logic designersPrerequisite:
• Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
• Familiarity with logic design (state machines and synchronous design)
• Basic knowledge of FPGA architecture and Xilinx implementation tools are helpful
• Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
Software Tools:
• Vivado® System Edition 2019.1
• Mentor Graphics Questa Advanced Simulator 10.4
Hardware:
• Architecture: 7 series and UltraScale FPGAs*
• Demo board: Kintex® UltraScale FPGA KCU105 board or Kintex-7 FPGA KC705 board*
Skills Gained: After completing this training, you will be able to:
• Describe and utilize the ports and attributes of the serial transceiver in Xilinx FPGAs and MPSoCs
• Effectively utilize the following features of the gigabit transceivers:
– 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
– Pre-emphasis and receive equalization
– Pre-emphasis and receive equalization
• Use the Transceivers Wizards to instantiate GT primitives in a design
• Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
• Use the IBERT design to verify transceiver links on real hardware
Lab Description:
Lab 1: Transceiver Core Generation
Use the Transceivers Wizard to create instantiation templates.
Lab 2: Transceiver Simulation
Simulate the transceiver IP by using the IP example design.
Lab 3: 64B/66B Encoding
Generate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results.
Lab 4: Transceiver Implementation
Implement the transceiver IP by using the IP example design.
Lab 5: IBERT Design
Verify transceiver links on real hardware.
Lab 6: Transceiver Debugging
Debug transceiver links.
Course Outline:
1. 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Overview
2. 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Clocking and Resets
3. Transceiver IP Generation – Transceiver Wizard
4. Transceiver Simulation
5. PCS Layer General Functionality
6. PCS Layer Encoding
7. Transceiver Implementation
8. PMA Layer Details
9. PMA Layer Optimization
10. Transceiver Test and Debugging
11. Transceiver Board Design Considerations
12. Transceiver Application Examples
