Embedded Systems Design

Start Date: 12/02/2024

Price 6,229 ILS

/ 18 Tcs

DURATION 3 Days

Course Overview

Learn general embedded concepts, tools, and techniques using the Vivado® Design Suite and Vitis™ unified software platform.

The emphasis is on:

Designing, expanding, and modifying embedded systems utilizing the features and capabilities of the Zynq® System on a Chip (SoC), Zynq UltraScale+™ MPSoC, or MicroBlaze™ soft processor
Adding and simulating AXI-based peripherals using bus functional model (BFM) simulation

What’s New for 2021.1

All labs have been updated to the latest software versions.

Who should attend?

Engineers who are interested in developing embedded systems with the Xilinx Zynq SoC, Zynq UltraScale+ MPSoC, and/or MicroBlaze soft processor core

Prerequisite:

FPGA design experience
Completion of the Designing FPGAs Using the Vivado Design Suite 1 course or equivalent knowledge of Xilinx Vivado software implementation tools
Basic understanding of C programming
Basic understanding of microprocessors
Some HDL modeling experience

Software Tools:

Vivado® Design Suite 2021.1
Vitis unified software platform 2021.1

Hardware:

Architectures: Zynq-7000 SoC (Cortex™-A9 processor), Zynq UltraScale+ MPSoC (Cortex-A53 and Cortex-R5 processors), and MicroBlaze processor*
Demo board: Zynq UltraScale+ MPSoC ZCU104 or Versal™ ACAP VCK190 board*

* This course focuses on the Zynq-7000 SoC and Zynq UltraScale+ MPSoC architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained: After completing this training, you will be able to:

Describe the various tools that encompass a Xilinx embedded design
Rapidly architect an embedded system containing a Cortex-A9/A53/R5 or MicroBlaze processor using the Vivado IP integrator and Customization Wizard
Develop software applications utilizing the Vitis unified software platform
Create and integrate an IP-based processing system component in the Vivado Design Suite
Design and add a custom AXI interface-based peripheral to the embedded processing system.
Simulate a custom AXI interface-based peripheral using verification IP (VIP)

Lab Description:

Driving the IP Integrator Tool
Driving the Vitis Software Development Tool
AXI: Transactions
Creating a New AXI IP with the Wizard
AXI: BFM Simulation Using Verification IP
MicroBlaze Processor Architecture Overview
Overview of the Zynq-7000 SoC architecture
Zynq UltraScale+ MPSoC Architecture Overview

Course Outline:

Embedded UltraFast Design Methodology
Outlines the different elements that comprise the Embedded Design Methodology
Overview of Embedded Hardware Development
Overview of the embedded hardware development flow
Driving the IP Integrator Tool
Describes how to access and effectively use the IPI tool
Overview of Embedded Software Development
Reviews the process of building a user application
Driving the Vitis Software Development Tool
Introduces the basic behaviors required to drive the Vitis tool to generate a debuggable C/C++ application
AXI: Introduction
Introduces the AXI protocol
AXI: Variations
Describes the differences and similarities among the three primary AXI variations
AXI: Transactions
Describes different types of AXI transactions
Introduction to Interrupts
Introduces the concept of interrupts, basic terminology, and generic implementation
Interrupts: Hardware Architecture and Support
Reviews the hardware that is typically available to help implement and manage interrupts
AXI: Connecting AXI IP
Describes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies
Creating a New AXI IP with the Wizard
Explains how to use the Create and Import Wizard to create and package an AXI IP
AXI: BFM Simulation Using Verification IP
Describes how to perform BFM simulation using the Verification IP
MicroBlaze Processor Architecture Overview
MicroBlaze Processor Block Memory Usage
Highlights how block RAM can be used with the MicroBlaze processor
Zynq-7000 SoC Architecture Overview
Zynq UltraScale+ MPSoC Architecture Overview