Price 4585+ VAT /15 Tcs
DURATION 6 Half Days

Course Overview

PCI Express is the open standards- based successor to PCI and its variants for server- and client-system I/O interconnects. Unlike PCI and PCI-X, which are based on 32- and 64-bit parallel buses, PCI Express uses high-speed serial link technology similar to that found in Gigabit Ethernet, Serial ATA (SATA), and Serial-Attached SCSI (SAS). PCI Express reflects an industry trend to replace legacy shared parallel buses with high-speed point-to-point serial buses.

In this training we will discuss and cover the following:
  • Packet switching benefits compared to shared busses are highlighted
  • The course explains the various traffic types that PCI Express supports
  • The use of virtual channels to match Quality of Service requirements is explained
  • The course describes the discovery sequence required to initialize the switches
  • The course details the various stages of the physical layer : 8b10b and 128/130b coding, scrambling, elastic buffer, clock recovery and link training sequence
  • The course highlight the differences between the 3 generations of PCI Express 

Prerequisite:

Experience of a high speed digital bus like PCI / PCI-X is strongly recommended.

Course Outline:

1. The Transition to Packet Switching

  • PCI bus limitations
  • The hub link bus
  • Solutions to increase the performance : differential  transmission, packet switching

2. Introduction to PCI Express

  • Overview
  • Topology
  • Layer protocol
  • Quality of Service
  • The physical layer

3. The Physical Layer

  • 8-bit / 10-bit coding
  • Scrambling
  • The ordered sets
  • Elastic buffer operation
  • Link training, detailed step-by-step sequence
  • Jitter budgeting and measurement
  • The electrical interface
  • Calibration channel characteristics

4. Power Management

  • Link state power management
  • PCI Power Management software interface
  •  Native PCI Express power management mechanisms
  • Power budgeting capability

5. Packet Routing

  • PCI basics
  • Operation of PCI-to-PCI transparent bridge
  • Packet routing by the address
  • Packet routing by the ID
  • Packet routed implicitly

6. TLP Acknowledgement

  • Acknowledgement objectives
  • Counters / timers present in the transmitter and the receiver
  • Sequences
  • Cut-through switches
  • PCI Express Interrupt Management

7. Quality of Service

  • Introduction, traffic differentiation
  • VC arbitration
  • Port arbitration, switch model

8. Flow Control

  • Overview, transmit credit principle
  • Related counters
  • Credit update frequency

9. Transaction Ordering

  • PCI Producer / Consumer model
  • Relaxed ordering permitted by PCI-X
  • PCI Express transaction ordering rules

10. Packet Format

  • Benefits of a packet oriented protocol
  • TLP format
  • DLLP format

 

11. Interrupt Management

  • Message Signaled Interrupts
  • PCI Express Interrupt Management

12. Error Management

  • General principles
  • PCI-like error management
  • PCI Express basic error management
  • PCI Express basic advanced error management

13. The Configuration Space

  • Root Complex Register Block [RCRB]
  • PCI Express enumeration
  • PCI-compatible configuration registers
  • Expansion ROMs

14. Differences between Gen1, Gen2 and Gen3

  • The new physical layer of GEN2 and GEN3 with a 128/130b encoding
  • The new protocol transactions
  • The new PCI Express Enhanced Configuration Access Mechanism

15. Debugging a PCI Express System

  • Compliance lists
  • The Serial Data Analyser from Lecroy, test of the physical layer
  • Protocol analyser / exercicer from Lecroy
  • Trace analysis

Day 4 (optional): Xilinx Specific ImplementationLab 1: Construction the PCIe Core

  • PCIe and Core Generator  overview
  • Connecting logic to the core – LocalLink
    • PCIe Link and System Interface Signals
    • Common Transaction Interface Signals
    • Transmit examples
    • Receive examples

Lab 2: Endpoint design and debugging

  • Designing the endpointapplication
  • Specification review
  • Selecting the appropriate core
  • Select appropriate parameters for the CORE Generator tool

Lab 3: PCIe core debugging

  • Simulating a PCIe Design
    • Simulation methods
    • Building testbenches
  • Debugging a PCIe core with ChipScope Pro
    • Use the ChipScope Pro tools to monitor the behavior of the core

Lab 4: Running the application

  • Configuration space exploring
    • Enumeration example learning
    • Interrupts and Advanced Error Reporting 
  • Host side application and drivers (optional)
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