Menu
- Designing with Verilog Duration: 4Start Date: 14/02/2023
- Designing with VHDL Duration: 4
- Doulos UVM Adopter Class Duration: 4Start Date: 29/03/2023
- Xilinx SystemVerilog for Design and Verification Duration: 4Start Date: 08/02/2022
Talk to us. About anything. Really. We’re sitting at a call center with literally one job – to answer any question you might have.
- Yitzhak Rabin 1
- Petah Tikva
- +972-3-9247781
Logtel – part of a leading group, designing the professions of the future
