- Designing with Verilog Duration: 4Start Date: 12/05/2025
- Designing with VHDL Duration: 4Start Date: 14/10/2025
- Doulos UVM Adopter Class Duration: 4Start Date: 11/03/2025
- Xilinx SystemVerilog for Design and Verification Duration: 4Start Date: 12/11/2025
Derech Yitzhak Rabin 1, Petah Tikva, ‘Global Towers’ complex
