Start Date: 29/03/2022
Course Overview
This course also includes a detailed discussion about proper PCB design techniques that enables designers to avoid common mistakes and get the most out of their FPGA interfaces.
A combination of modules and labs allow for practical hands-on application of the principles taught.
Who should attend?
• Xilinx hardware designersPrerequisite:
• Essentials of FPGA Design course
• Intermediate VHDL or Verilog knowledge Software Tools: ISE Design Suite 14.x
Software Tools:
• VIVADO Design Suite 2013.3
Hardware:
• ZYNQ-7000
• Demo board: ZC706 / (KC705)
Skills Gained: After completing this training, you will be able to:
After completing this training, you will be able to:
• Describe the functionality of transceivers, PCIe blocks and memory interfaces
• Configure the corresponding wizards to design high-speed interfaces
• Simulate and implement high-speed interfaces
• Start practical work with high-speed interfaces
• Describe challenges and solutions for successful powering and interfacing high-speed interfaces on PCB level
• Apply high-speed interface specific signal integrity rules in PCB design
Course Outline:
1. Introduction to high-speed connectivity
2. Zynq Board Design
– General design constraints
– Signal integrity on chip level (IO region)
– Power options, requirements and solutions
– Power estimation in XPE vs. Power calculations in Vivado
– Powering transceivers – requirements and solutions
– Powering memory interfaces – requirements and solutions
– Board design for Agile Mixed Signal
– Signal integrity on board level
– Board design checklist
3. Serial transceiver
– Transceiver overview (7 series FPGAs and Zynq 7000)
– Basic principles and solutions in serial transmission
– Transceiver design
Lab1: Generating transceiver design
– Simulation and implementing transceiver interfaces
Lab2: Transceiver simulation and implementation
– Debugging transceiver interfaces
Lab3: IBERT
– PCIe Basics
– Xilinx PCIe solutions
– PCIe endpoint design
Lab1: Generating PCIe endpoint
– Simulation and Implementation PCIe interfaces
Lab2: PCIe endpoint simulation and implementation
– Usage of PCIe endpoint in application
Lab3: PCIe endpoint in real system with ZC706 / (KC-705) board
5. Memory Interfaces
– Memory devices overview
– Xilinx memory interface solutions
– DDR3 design
Lab1: Generating DDR3 controller
– Simulation and implementation memory interfaces
Lab2: DDR3 interface simulation and implementation
– Implementing memory interfaces
Lab3: Verification DDR3 interface on real hardware