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- Signal Integrity and Board Design Using HyperLynx Duration: 4Start Date: 19/11/2023
- PCIe Gen1.X to 4.X Duration: 4Start Date: 17/07/2022
- Designing with Xilinx Serial Transceivers Duration: 2Start Date: 22/05/2023
- Designing with PCI Express Gen 1.x – 4.0 Duration: 4Start Date: 15/10/2023
- USB Architecture Duration: 2Start Date: 24/04/2023
- Advanced VHDL Duration: 2
- Designing with the UltraScale and UltraScale+ Architectures Duration: 2Start Date: 03/03/2022
- High-Level Synthesis with the Vitis HLS Tool Duration: 3Start Date: 15/10/2023
- Designing FPGAs Using the Vivado Design Suite 2 Duration: 4Start Date: 21/11/2023
