- Signal Integrity and Board Design Using HyperLynx Duration: 4Start Date: 17/09/2025
- PCIe Gen1.X to 4.X Duration: 4Start Date: 06/07/2025
- Designing with Xilinx Serial Transceivers Duration: 2Start Date: 16/10/2025
- USB Architecture Duration: 2Start Date: 08/07/2025
- Advanced VHDL Duration: 2Start Date: 21/08/2025
- Designing with the UltraScale and UltraScale+ Architectures Duration: 2Start Date: 13/07/2025
- C-based Design: High-Level Synthesis with the Vivado HLx Tool Duration: 3Start Date: 17/12/2025
- High-Level Synthesis with the Vitis HLS Tool Duration: 3Start Date: 04/11/2025
- Designing FPGAs Using the Vivado Design Suite 2 Duration: 4Start Date: 23/11/2025
