- Signal Integrity and Board Design Using HyperLynx Duration: 4Start Date: 11/02/2025
- PCIe Gen1.X to 4.X Duration: 4Start Date: 17/07/2022
- Designing with Xilinx Serial Transceivers Duration: 2Start Date: 22/05/2023
- USB Architecture Duration: 2Start Date: 24/04/2023
- Advanced VHDL Duration: 2Start Date: 10/02/2025
- Designing with the UltraScale and UltraScale+ Architectures Duration: 2Start Date: 03/03/2022
- C-based Design: High-Level Synthesis with the Vivado HLx Tool Duration: 3Start Date: 11/02/2025
- High-Level Synthesis with the Vitis HLS Tool Duration: 3Start Date: 26/05/2024
- Designing FPGAs Using the Vivado Design Suite 2 Duration: 4Start Date: 07/05/2025
Derech Yitzhak Rabin 1, Petah Tikva, ‘Global Towers’ complex
